The present invention relates to a semiconductor device fabrication method.
When a semiconductor device has the shorter channel length decreased by the micronization, short channel effect becomes conspicuous, and the MOS transistors cannot normally operate. As a technique for preventing the short channel effect, semiconductor devices having extension source/drain structure are recently noted.
When the extension region of a PMOS transistor is formed, the region for an NMOS transistor to be formed in is covered with a photoresist film, and a dopant is implanted into the semiconductor substrate with the gate electrode and a photoresist film as the mask to form the extension region. Then, the photoresist film is released.
On the other hand, when the extension region of the NMOS transistor is formed, the region for the PMOS transistor formed in is covered with a photoresist film, and a dopant is implanted into the semiconductor substrate with the gate electrode and the photoresist film as the mask to form the extension region. Then, the photoresist film is released.
The MOS transistor of the extension source/drain structure can suppress the short channel effect, which makes it possible to provide further micronized semiconductor devices.
Following references disclose the background art of the present invention.
[Patent Reference 1]
Specification of Japanese Patent Application Unexamined Publication No. Hei 6-204243
[Patent Reference 2]
Specification of Japanese Patent Application Unexamined Publication No. Hei 6-209081
However, when a photoresist film is removed, ashing processing and chemical liquid processing are performed. In the ashing processing, the extension region is oxidized. In the chemical liquid processing, the extension region is oxidized and etched. Accordingly, the electric resistance of the extension region tends to become higher. A technique for suppressing the electric resistance of the extension region to be low is expected.